FH-Prof. DI Dr. Peter Rössler
Program Director Bachelor Electronics and Business
Research Focus Manager Embedded Systems & Cyber-Physical Systems
CV
Publications
Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation
Programmable Logic Devices – Key Components for Today's and Tomorrow's Electronic-Based Systems
FIJI – Fault InJection Instrumenter
A Netlist-level Fault-injection Tool for FPGAs
Ein flexibler Gateway-Knoten für Netzwerke im Automobil
Design Considerations for Scalable High Performance Vision Systems Embedded in Industrial Print Inspection Machines
Field Programmable Analog Circuits and Arrays – An Overview
Evaluation of Open-Source Linear Algebra Libraries targeting ARM and RISC-V Architectures
Survey and Comparison of Digital Logic Simulators
Open-Source RISC-V Processor IP Cores for FPGAs – Overview and Evaluation
Checking Application-level Properties Using Assertion Synthesis
Innovative Plattformen für Elektronische Systeme (INES)
Evaluation of Open-Source Linear Algebra Libraries in Embedded Applications
A Model Railway based Demonstrator for Saftey-Critical Systems
Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu
A FPGA-based Demonstrator for Safety-Critical Applications
Logic Synthesis of Assertions for Saftey-critical Applications
Entwicklung eines flexibel in der Lehre einsetzbaren Designflows für digitale Mikrochips
Considerations on Teaching Digital ASIC Design
On Automated Generation of Checker Units from Hardware Assertion Languages
A Low-cost Sound Generator for an Electric Quad Bike
A methodology for remote debug, test and maintenance based on IEEE1588
Ausgelagerte Uhrensynchronisation für verteilte eingebettete Systeme
Weltweit kleinste, voll integrierte Lösung zur Uhrensynchronisation nach IEEE 1588 auf Schicht 2
Remote LAB infrastructure for Distance Learning Courses at the Undergraduate Level in Embedded Systems Design
On-chip Hardware Support for a Radically New Approach to Coordinated Debug of Networked Embedded Systems
Evaluation of an Esterel-based Hardware/Software Co-Design Flow
Nicht-intrusive Uhrensynchronisation nach IEEE 1588 für verteilte, eingebettete Systeme via IEEE 802.3/Ethernet
Background IEEE 1588 Clock Synchronization over IEEE 802.3/Ethernet, ISPCS 2008
Development of a Flexible Gateway Platform for Automotive Networks
Development of a Data Collection Platform
Performance Benchmark of DSP and FPGA Implementations of Low-Level Vision Algorithms
Optimization and Benchmark of Vision Algorithms on a DSP
Entwicklung eines Satellitenmodems
Evaluierung eines Esterel-basierenden Hardware/Software Co-Design Flows
Hochgeschwindigkeitskamera mit intelligenter Datenvorverarbeitung
Architecture for Hardware-driven Image Inspection based on FPGAs
Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu
Logic Synthesis of Assertions for Saftey-critical Applications
Considerations on Teaching Digital ASIC Design
FlexRay (Chapter 44)